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AEsqu's avatar
AEsqu
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4 years ago

rapid recompile (signal tap logic analyzer flow) : out of memory

When I use the rapid recompile (signal tap logic analyzer flow, quartus std 21.1.0 Build 842) : out of memory (even with 64 GB or RAM). Cyclone V FPGA, used at around 50%. When I use the normal c...
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
4 years ago

Hi Alex,


Could you provide a sample design with the problem for testing?


Thanks

Best Regards

Sheng


  • AEsqu's avatar
    AEsqu
    Icon for Contributor rankContributor
    4 years ago

    Hi Sheng,

    I cannot.

    Alex.