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ZhaoyangDu's avatar
ZhaoyangDu
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3 years ago

R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example, VCS simulation failed.

I can't get the original R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example's VCS simulaiton passed. The error is compilation error : "[PE_CDB] corrupted data block" shown in the following figure.

I didn't change any configuration of the PCIE parameters. I execute the vcs_setup.sh according to the "R-tile Avalon® Streaming Intel®FPGA IP for PCI Express* Design Example User Guide, Updated for Intel® Quartus® Prime Design Suite: 22.2" document. The PCIE generation is gen5. I use Intel Quartus Prime Pro 22.2. The targetd device is AGIB027R29A1E2VR0. The OS is CentOS 7.9.2009.

Please help me check if anything was wrong.

14 Replies

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi,

    Can you try to run it at latest version of Quartus v22.4 and see if the same error still able to replicate ?
    Hoping to hear back from you.

    Regards,

    Wincent_Intel

    • ZhaoyangDu's avatar
      ZhaoyangDu
      Icon for New Contributor rankNew Contributor
      3 years ago

      Hi Wincent_Intel，

      I can't try this on Quartus Prime Pro v22.4. I have to use Quartus v22.2. Please help fix or provide a workaround on Quartus v22.2. Thank you.

      Regards,

      Zhaoyang Du

    • ZhaoyangDu's avatar
      ZhaoyangDu
      Icon for New Contributor rankNew Contributor
      3 years ago

      Hi，

      I have used exactly the same command as in the link you provided and encountered the same error in this post.

      Regards,

      Zhaoyang Du

    • ZhaoyangDu's avatar
      ZhaoyangDu
      Icon for New Contributor rankNew Contributor
      3 years ago

      Hi,

      I used exactly the same cmd as in the link when I encountered the errors in this post.

      sh vcs_setup.sh USER_DEFINED_COMPILE_OPTIONS="" USER_DEFINED_ELAB_OPTIONS="-xlrm\ uniq_prior_final\ -debug_access+all" USER_DEFINED_SIM_OPTIONS="" TOP_LEVEL_NAME="pcie_ed_tb" | tee simulation.log

      Regards,

      Zhaoyang Du

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi,


    Please accept my apology for late reply due to the Lunar New Year holiday.

    Can I know your device OPN number ?

    I will try to see if I am able to replicate the issue on my place.


    Regards,

    Wincent_Intel


  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi,


    Please ignore my previous reply. The device OPN is there.

    I will try to replicate this issue on my place.


    Get back to you as soon as possible.


    Regards,

    Wincent_Intel


  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi,


    Are you tested using A0 silicon version or B0 silicon version ?


    Regards,

    Wincent_Intel


    • ZhaoyangDu's avatar
      ZhaoyangDu
      Icon for New Contributor rankNew Contributor
      3 years ago

      Hi,

      What is A0 and B0 silicon version? By the way, the FPGA device is AGIB027R29A1E2VR0.

      Regards,

      Zhaoyang Du

    • ZhaoyangDu's avatar
      ZhaoyangDu
      Icon for New Contributor rankNew Contributor
      3 years ago

      Hi，

      We use the A0 silicon version. Please continue to help find the problems of this post. Thanks.

      Regards，

      Zhaoyang Du

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi,


    Please allow me to have more time to investigate on this issue.

    Get back to you soon as possible.


    Regards,

    Wincent_Intel


  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi,


    I had run it, But i dont see a similar issue as yours.

    Can you please regenerate the whole design and try to run it again ?



    Regards,

    Wei Chuan


  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi,

    I wish to follow up with you about this case.

    Do you have any further questions on this matter ?

    ​​​​​​​Else I would like to have your permission to close this forum ticket

    Regards,

    Wincent_Intel


  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi

    We have not hear from you and this Case is idling. It is not recommended to idle for too long.

    Therefore following our support policy, I have to put this case in close status. My apologies if any inconvenience cause

    Hence, This thread will be transitioned to community support.

    If you have a new question, feel free to open a new thread to get support from Intel experts.

    Otherwise, the community users will continue to help you on this thread. Thank you

    If you feel your support experience was less than a 9 or 10,

    please allow me to correct it before closing or let me know the cause so that I may improve your future support experience.

    Regards,

    Wincent_Intel