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ZhaoyangDu
New Contributor
New ContributorR-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example, VCS simulation failed.
I can't get the original R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example's VCS simulaiton passed. The error is compilation error : "[PE_CDB] corrupted data block" shown in th...
Wincent_Altera
Regular Contributor
Regular ContributorHi,
Can you run the command provided in below KDB and see if the same error still able to obtain ?
Regards,
Wincent_Intel
ZhaoyangDuNew Contributor
New ContributorHi,
I used exactly the same cmd as in the link when I encountered the errors in this post.
sh vcs_setup.sh USER_DEFINED_COMPILE_OPTIONS="" USER_DEFINED_ELAB_OPTIONS="-xlrm\ uniq_prior_final\ -debug_access+all" USER_DEFINED_SIM_OPTIONS="" TOP_LEVEL_NAME="pcie_ed_tb" | tee simulation.log
Regards,
Zhaoyang Du
