Forum Discussion
ZhaoyangDu
New Contributor
3 years agoR-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example, VCS simulation failed.
I can't get the original R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example's VCS simulaiton passed. The error is compilation error : "[PE_CDB] corrupted data block" shown in th...
Wincent_Altera
Regular Contributor
3 years agoHi,
I had run it, But i dont see a similar issue as yours.
Can you please regenerate the whole design and try to run it again ?
Regards,
Wei Chuan