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ZhaoyangDu's avatar
ZhaoyangDu
Icon for New Contributor rankNew Contributor
3 years ago

R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example, VCS simulation failed.

I can't get the original R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example's VCS simulaiton passed. The error is compilation error : "[PE_CDB] corrupted data block" shown in th...
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,

Can you try to run it at latest version of Quartus v22.4 and see if the same error still able to replicate ?
Hoping to hear back from you.

Regards,

Wincent_Intel

  • ZhaoyangDu's avatar
    ZhaoyangDu
    Icon for New Contributor rankNew Contributor
    3 years ago

    Hi Wincent_Intel，

    I can't try this on Quartus Prime Pro v22.4. I have to use Quartus v22.2. Please help fix or provide a workaround on Quartus v22.2. Thank you.

    Regards,

    Zhaoyang Du