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ZhaoyangDu
New Contributor
New ContributorR-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example, VCS simulation failed.
I can't get the original R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example's VCS simulaiton passed. The error is compilation error : "[PE_CDB] corrupted data block" shown in th...
Wincent_Altera
Regular Contributor
Regular ContributorHi,
Are you tested using A0 silicon version or B0 silicon version ?
Regards,
Wincent_Intel
ZhaoyangDuNew Contributor
New ContributorHi,
What is A0 and B0 silicon version? By the way, the FPGA device is AGIB027R29A1E2VR0.
Regards,
Zhaoyang Du
