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Honored Contributor
Honored ContributorPhase lock loop
I want to implement a phase lock loop in fpga , altera(cyclone II). The internal clock is 50 MHZ. but my input clock is 60 HZ. How i should implement pll in this case???
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Altera_ForumYou didn't mention the intended output of the PLL (frequency, waveform). In power electronic applications, a 50/60 Hz PLL with quadrature sine output is a common building block. It can be implemented with a NCO, phase detector (multiplier with averager/integrator) and a PI controller. In contrast to the high frequency analog PLL provided for FPGA clocking, the complete PLL function is performed by digital signal processing. Thus it's called digital or all digital PLL (DPLL/ADPLL).
- Altera_Forum
My output should be same as input(60 HZ). But fpga has in built pll, whose internal clock works at Mhz. So Hz and Mhz cant be synchronized.
I was trying to implement in zero buffer mode using a[/U][/U]ltpll megafunction But its input range is in MHz. It is possible for me to implement in fpga reconfig methods. - Altera_Forum--- Quote Start --- But fpga has in built pll, whose internal clock works at Mhz. So Hz and Mhz cant be synchronized. --- Quote End --- How do you want to achieve synchronization? Did you notice the PLL input frequency range? Minimum input frequency, set by the PFD properties, is 10 MHz. That's why I suggested an ADPLL design.
- Altera_Forum
Thank u so much for the reply. it is possible for me to implement ADPLL in fpga, using megafunction wizard? If not , can we code in vhdl.
Your help is appreciated.. - Altera_Forum
There's no Altera MegaFunction providing ADPLL functionality. There has been a previous forum discussion related to an ADPLL code sourced from Best's PLL text book, if I understand right. The original poster said it doesn't work. Apart from this particular code, it's of course possible to implement the ADPLL concept from literature in VHDL. I have implemented a PLL as sketched in my above post. But it's part of a larger customer design and neither dedicated to the public domain nor written to be instructive.
http://www.alteraforum.com/forum/showthread.php?t=3310 - Altera_Forum
what is diff between dpll and adpll?
How we can implement adpll in fpga? Using reconfig methods can we implement adpll at 60 HZ input freq and output freq is also same. - Altera_Forum
In Best's PLL book, ADPLL is designating PLLs with a software VCO (NCO), while DPLL means PLLs with analog VCO and digital phase detector. In this view, the PLLs implemented in Altera FPGAs are DPLLs, too. But in other literature, the term DPLL is also used for software PLLs
The built-in FPGA PLLs are only suited for input frequencies in the MHz range by the design of their phase detector and dimensioning of the PLL loop filter. There's effectively no chance to synchronize them to 60 Hz input. I previously mentioned the basic components of an ADPLL design. Details can be found in literature, e.g. Roland E. Best, phase-locked loops, design, simulation and applications. Unfortunately, I don't have a ready-to-use HDL code example. - Altera_Forum
1.Does Altera fpga DE2 board has in built analog to digital converter?
2.I want to synchronize 60 hz input , from the following which will be the suitable phase frequency detector for my requirement? a. Flip-flop Counter PD b.Nyquist Rate Phase Detector c.Zero-Crossing Phase Detector d.Hilbert Transform Phase Detector e.Digital-Averaging Phase Detector Your help is really appreciated - Altera_Forum
Phase detector selection mainly depends on the type of input signal, that you didn't mention yet. For an analog input signal (sine waveform), I prefer either a simple multiplier ("Nyquist rate detector") or a quadrature multiplier with amlitude scaling ("Averaging phase detector"). For a digital input clock, a FF counter or XOR phase detector could be used.
I just noticed, that Altera (previously?) had an adpll reference design shipped with the NCO IP. The description briefly mentions the involved building blocks: http://www.altera.com/products/ip/altera/t-alt-adpll.html - Altera_Forum
My input is sine wave which is 60 hz. my output should be exactly synchronized with output having 60 Hz digital output.
The input should first be given to analog to didgital converter right. Does altera fpga support inbuilt analog to digital converter??
