Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Phase lock loop

I want to implement a phase lock loop in fpga , altera(cyclone II). The internal clock is 50 MHZ. but my input clock is 60 HZ. How i should implement pll in this case???
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

In Best's PLL book, ADPLL is designating PLLs with a software VCO (NCO), while DPLL means PLLs with analog VCO and digital phase detector. In this view, the PLLs implemented in Altera FPGAs are DPLLs, too. But in other literature, the term DPLL is also used for software PLLs

The built-in FPGA PLLs are only suited for input frequencies in the MHz range by the design of their phase detector and dimensioning of the PLL loop filter. There's effectively no chance to synchronize them to 60 Hz input.

I previously mentioned the basic components of an ADPLL design. Details can be found in literature, e.g. Roland E. Best, phase-locked loops, design, simulation and applications. Unfortunately, I don't have a ready-to-use HDL code example.