Altera_Forum
Honored Contributor
Honored ContributorPhase lock loop
I want to implement a phase lock loop in fpga , altera(cyclone II). The internal clock is 50 MHZ. but my input clock is 60 HZ. How i should implement pll in this case???
Forum Discussion
Altera_ForumHonored Contributor
Honored ContributorPhase detector selection mainly depends on the type of input signal, that you didn't mention yet. For an analog input signal (sine waveform), I prefer either a simple multiplier ("Nyquist rate detector") or a quadrature multiplier with amlitude scaling ("Averaging phase detector"). For a digital input clock, a FF counter or XOR phase detector could be used.
I just noticed, that Altera (previously?) had an adpll reference design shipped with the NCO IP. The description briefly mentions the involved building blocks: http://www.altera.com/products/ip/altera/t-alt-adpll.html
