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Altera_Forum
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15 years ago

Phase lock loop

I want to implement a phase lock loop in fpga , altera(cyclone II). The internal clock is 50 MHZ. but my input clock is 60 HZ. How i should implement pll in this case???
Altera_Forum's avatar
Altera_Forum
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15 years ago

You didn't mention the intended output of the PLL (frequency, waveform). In power electronic applications, a 50/60 Hz PLL with quadrature sine output is a common building block. It can be implemented with a NCO, phase detector (multiplier with averager/integrator) and a PI controller. In contrast to the high frequency analog PLL provided for FPGA clocking, the complete PLL function is performed by digital signal processing. Thus it's called digital or all digital PLL (DPLL/ADPLL).