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Honored Contributor
Honored ContributorPhase lock loop
I want to implement a phase lock loop in fpga , altera(cyclone II). The internal clock is 50 MHZ. but my input clock is 60 HZ. How i should implement pll in this case???
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Altera_ForumHonored Contributor
Honored ContributorMy input is sine wave which is 60 hz. my output should be exactly synchronized with output having 60 Hz digital output.
The input should first be given to analog to didgital converter right. Does altera fpga support inbuilt analog to digital converter??
