Altera_Forum
Honored Contributor
Honored ContributorPhase lock loop
I want to implement a phase lock loop in fpga , altera(cyclone II). The internal clock is 50 MHZ. but my input clock is 60 HZ. How i should implement pll in this case???
Forum Discussion
Altera_ForumHonored Contributor
Honored Contributorwhat is diff between dpll and adpll?
How we can implement adpll in fpga? Using reconfig methods can we implement adpll at 60 HZ input freq and output freq is also same.
