Altera_Forum
Honored Contributor
Honored ContributorPhase lock loop
I want to implement a phase lock loop in fpga , altera(cyclone II). The internal clock is 50 MHZ. but my input clock is 60 HZ. How i should implement pll in this case???
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Altera_ForumHonored Contributor
Honored ContributorThank u so much for the reply. it is possible for me to implement ADPLL in fpga, using megafunction wizard? If not , can we code in vhdl.
Your help is appreciated..
