Phase lock loop

There's no Altera MegaFunction providing ADPLL functionality. There has been a previous forum discussion related to an ADPLL code sourced from Best's PLL text book, if I understand right. The original poster said it doesn't work. Apart from this particular code, it's of course possible to implement the ADPLL concept from literature in VHDL. I have implemented a PLL as sketched in my above post. But it's part of a larger customer design and neither dedicated to the public domain nor written to be instructive.