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Altera_Forum's avatar
Altera_Forum
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15 years ago

Phase lock loop

I want to implement a phase lock loop in fpga , altera(cyclone II). The internal clock is 50 MHZ. but my input clock is 60 HZ. How i should implement pll in this case???
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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But fpga has in built pll, whose internal clock works at Mhz. So Hz and Mhz cant be synchronized.

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How do you want to achieve synchronization? Did you notice the PLL input frequency range? Minimum input frequency, set by the PFD properties, is 10 MHz. That's why I suggested an ADPLL design.