Altera_Forum
Honored Contributor
Honored ContributorPhase lock loop
I want to implement a phase lock loop in fpga , altera(cyclone II). The internal clock is 50 MHZ. but my input clock is 60 HZ. How i should implement pll in this case???
Forum Discussion
Altera_ForumHonored Contributor
Honored Contributor1.Does Altera fpga DE2 board has in built analog to digital converter?
2.I want to synchronize 60 hz input , from the following which will be the suitable phase frequency detector for my requirement? a. Flip-flop Counter PD b.Nyquist Rate Phase Detector c.Zero-Crossing Phase Detector d.Hilbert Transform Phase Detector e.Digital-Averaging Phase Detector Your help is really appreciated
