Making Nodes visible to SignalTap

Unfortunately that doesn't seem to work:

(* noprune *) bit [9:0] vic_screen_last_active_hpixel;
(* noprune *) bit [9:0] vic_last_active_hpixel;
(* noprune *) bit [9:0] vic_screen_hstart_pixels;
(* noprune *) bit [9:0] vic_last_screen_hpixel;
(* noprune *) bit [9:0] vic_horiz_border_pixels;

As you can see, the existing nodes in SignalTap turned red and I cannot locate the new ones marked with (* noprune *) :

I tried /* synthesis keep */ and /* synthesis preserve */ from the notes I'd made some time ago - but in my notes I stated that I had problems trying to get nodes to appear and the only way I could get it to work was to make output signals in the module header instead.

Does it only work with the reg keyword perhaps?

Yes I normally just do the "Start Analysis and Elaboration" when adding new nodes, to get SignalTap to have visibility of them. Right now I'm compiling the whole thing, shutting down SignalTap and restarting SignalTap but it still won't show those nodes with the Pre-Synthesis filter.

I think the Virtual pin assignment would take longer to do as well - these days I edit my Verilog with Notepad++ so I have access to keyboard macros and the likes to speed up editing.

The only reason I mentioned Notepad is that I find editing text faster than going into the Quartus UI screens. Just saying that if I can "decorate" registers/nodes withing the Verilog text, that's easier than fiddling with the Assignment Editor.. However.. I do seem to have hit the pin limit where I may need to do what you suggested anyway:

What is my logic connected to? Well.. I had hardcoded a load of constants that need to become variable. Once I did that, the logic didn't seem to work the way I expected it to so I thought I would "promote" the nodes to outputs so I can see what values they are taking on in SignalTap..

Maybe I have far too many interdependencies here and perhaps I need to take a step back and simplify what I have.

The last 5 signals I refer to in my VGAController module - it decides where to paint a border or a screen background.. as the old Commodore Vic 20 used to.

I know what I am doing it bad because I am including so much arithmetic now. It wouldn't have mattered with the constants.. but pretty bad to implement that complicated mess in logic.

When you say "registering those signals", what do you actually mean, sorry?

Here's another case for example:

bit [7:0] vic_screen_lines;
assign vic_screen_lines = vicScreenCharHeight << 3; 

I have other assign statements that use vic_screen_lines but I cannot view them in SignalTap.

I tried this too but it made no difference:

(* noprune *) reg [7:0] vic_screen_lines;

No, the issue with SignalTap not showing the values is not resolved. I am busy trying to fix my logic overall - I can still only track outputs from my modules. I cannot track other nodes such as the ones mentioned earlier.