Forum Discussion
ContributorMaking Nodes visible to SignalTap
I tried (* preserve_for_debug *) in VgaDisplay.sv but that still won't show vic_screen_lines in STP. I tried "Design Filter (all names)" as well - it still doesn't appear when I click List.
It is not listed in the 2 optimization result reports for removal, I can't find it in the compilation output, and I certainly can't see it in the RTL Viewer so it must have been removed somehow.
BUT.. I have just this minute tried searching for *vic_screen_lines* - and it appears! So I will have to remind myself to always use the asterisks either side of the node. I feel so stupid now - thank you for joining on me on this journey.
Always surround with asterisks, Sparky! Always!
Super ContributorHi,
the only explanation why noprune doesn't work for these nodes is that they are not registers or not reside in the respective module.
E.g. assign vic_screen_lines = vicScreenCharHeight << 3; surely doesn't infer registers or combinational logic cells, just alias bits for vicScreenCharHeight, whatever it is. If it's a constant, it won't be accessible by Signaltap.
As stated by sstrell, storing it in a register with noprune attribute will surely make it visible, except for the lower bits which are constantly zero and thus discarded.
Regarding pin limit for port signal, you might declare the respective ports as virtual pins in assignment editor, doesn't consume pins but keeps the port.
Regards
Frank
