Quartus Prime Lite 25.1 - Issue with the Verilog generate loops

Hi!

I believe, this is the same issue mentioned here, or at least its sibling. Long story short, here is a snippet from the IEEE Std 1364™-2005 standard, page 185:

module addergen1 (co, sum, a, b, ci);
    parameter SIZE = 4;
    output [SIZE-1:0] sum;
    output co;
    input [SIZE-1:0] a, b;
    input ci;
    wire [SIZE :0] c;
    wire [SIZE-1:0] t [1:3];
    genvar i;
    assign c[0] = ci;

    // Hierarchical gate instance names are:
    // xor gates: bit[0].g1 bit[1].g1 bit[2].g1 bit[3].g1
    // bit[0].g2 bit[1].g2 bit[2].g2 bit[3].g2
    // and gates: bit[0].g3 bit[1].g3 bit[2].g3 bit[3].g3
    // bit[0].g4 bit[1].g4 bit[2].g4 bit[3].g4
    // or gates: bit[0].g5 bit[1].g5 bit[2].g5 bit[3].g5
    // Generated instances are connected with
    // multidimensional nets t[1][3:0] t[2][3:0] t[3][3:0]
    // (12 nets total)
    
    for(i=0; i<SIZE; i=i+1) begin:bit
        xor g1 ( t[1][i], a[i], b[i]);
        xor g2 ( sum[i], t[1][i], c[i]);
        and g3 ( t[2][i], a[i], b[i]);
        and g4 ( t[3][i], t[1][i], c[i]);
        or g5 ( c[i+1], t[2][i], t[3][i]);
    end

    assign co = c[SIZE];
endmodule

Quartus Prime 25.1std.0 Build 1129 10/21/2025 SC Lite Edition reports the error 10170 when attempting to compile this module:

Error (10170): Verilog HDL syntax error at main.v(22) near text: "for"; expecting "endmodule". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

Error (10170): Verilog HDL syntax error at main.v(23) near text: ")"; expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

Error (10170): Verilog HDL syntax error at main.v(28) near text: "end"; expecting "endmodule". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

Error (10112): Ignored design unit "addergen1" at main.v(1) due to previous errors

It accepts it, though, if to embrace the generating loop into "generate/endgenerate" framing. 

The Verilog version in the project settings is "Verilog-2001". Changing it to "System Verilog" has no impact on the behavior.

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For comparison, I fed this exact snippet to the Questa Altera Starter FPGA Edition-64 2025.2 and it had no problems with it.

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So my question is: "What is the root cause of this misbehaving?". Am I understanding the standard wrong? Ot is it some peculiarity of the Quartus itself? 

Thanks in advance!