Quartus Prime Lite 25.1 - Issue with the Verilog generate loops

Hi ElShang,

there's a change in generate block specification from Verilog 2001 to 2005. Verilog 2005 states (12.4 Generate constructs, page 181)

The keywords generate and endgenerate may be used in a module to define a generate region. A generate
region is a textual span in the module description where generate constructs may appear. Use of generate
regions is optional. There is no semantic difference in the module when a generate region is used.

Verilog 2001 requires generate - endgenerate (12.1.3 Generated instantiation, page 169)

All generate instantiations are coded within a module scope and require the keywords generate - endgener
ate. 

Quartus Prime Std implements only Verilog 2001 and not exactly defined Subset of System Verilog.

In Quartus Prime Pro, the keywords are optional as you expect.

Regards
Frank