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vilem's avatar
vilem
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1 month ago

DisplayPort Sink (Quartus 18.1) – horizontal pixel offset.

We are experiencing an issue with the DisplayPort Sink IP core (Quartus Prime 18.1), where the captured video stream becomes horizontally shifted after some runtime. The system works correctly after reset, but after a variable period (typically several minutes), the image suddenly shifts horizontally by a constant number of pixels (hundreds of pixels). The image remains stable but shifted. After longer time (tens of minutes), the image may spontaneously recover, and the cycle repeats. This behavior only appears when the input signal is routed through a DisplayPort optical extender (G&D). Without the extender, the system operates correctly and indefinitely stable.

This system design is constrained to Quartus 18.1 (cannot migrate easily) - We are primarily looking for a workaround or confirmation of known limitation - Not asking for redesign or migration unless necessary

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4 Replies

  • VenT_Altera's avatar
    VenT_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    1 month ago

    Hi vilem

    Thank you for your question. I will go through your enquiry and get back to you soon.  

    Thanks.
    Best Regards,
    Ven 

  • vilem's avatar
    vilem
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    1 month ago

    In the meantime we have found, that a resetting the Clock Recovery Core immediately restores proper image alignment. Is there any newer version of CRC which is usable for Quartus 18.1 ?

    Thanks

    Vilem

     

  • VenT_Altera's avatar
    VenT_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    25 days ago

    Hi vilem, 

     

    My apologies for the delayed reply, and thanks for the update — the CRC reset restoring alignment is a very useful finding. 

    Regarding a newer CRC on Quartus 18.1, the Clock Recovery Core is delivered with the design example for that Quartus release and is not supported as a standalone upgrade from a newer Quartus into 18.1. As a runtime workaround, automating the CRC reset you already validated (when the alignment is wrong). 

     

    I have the following questions to clarify: 

    1. What is the device family/OPN, link rate and lane count set?  
    2. When the image is shifted, do MSA values (HSTART, HTOTAL, HWIDTH) stay the same, or do they change? Also, do msa_lock / rx_vid_locked / BER counters glitch at that moment? 
    3. While the image is shifted, does the DP Sink still declare video lock (rx_vid_locked asserted)?

     

    On the extender: try a lower negotiated link rate or fewer lanes, check the firmware, since the failure only appears with the extender. 

     

    Thanks. 

    Best Regards, 

    Ven

    • vilem's avatar
      vilem
      Icon for New Contributor rankNew Contributor
      24 days ago

      Hi Ven,

      ad 1) DP1.2-VisionXG-Fibers(S), 4 optical pairs, HBR2

      ad 2) When the image is shifted all MSA values stay the same. 

      ad 3) When the image is shifted DP Sink still declare video lock.

      In the meantime, we found that CRC itself amplifies the consequences of the issue cause. When we removed CRC from the design the frames did not stay shifted. There is only 1 frame shifted and the following frames are correct. The damaged frame is indicated in changing of SOL/SOF, EOL/EOF signals on the DP Sink output.

      Thanks

      Best Regards,

      Vilem