Forum Discussion
ContributorMaking Nodes visible to SignalTap
I tried (* preserve_for_debug *) in VgaDisplay.sv but that still won't show vic_screen_lines in STP. I tried "Design Filter (all names)" as well - it still doesn't appear when I click List.
It is not listed in the 2 optimization result reports for removal, I can't find it in the compilation output, and I certainly can't see it in the RTL Viewer so it must have been removed somehow.
BUT.. I have just this minute tried searching for *vic_screen_lines* - and it appears! So I will have to remind myself to always use the asterisks either side of the node. I feel so stupid now - thank you for joining on me on this journey.
Always surround with asterisks, Sparky! Always!
Super Contributorregisters that are only used for Signaltap can be prevented from being discarded during synthesis by noprune synthesis attributes, detail description in Quartus handbook, chapter Quartus Integrated Synthesis.
Verilog-2001 and SystemVerilog:
(* noprune *) reg my_reg;
SparkyNZUnfortunately that doesn't seem to work:
(* noprune *) bit [9:0] vic_screen_last_active_hpixel; (* noprune *) bit [9:0] vic_last_active_hpixel; (* noprune *) bit [9:0] vic_screen_hstart_pixels; (* noprune *) bit [9:0] vic_last_screen_hpixel; (* noprune *) bit [9:0] vic_horiz_border_pixels;As you can see, the existing nodes in SignalTap turned red and I cannot locate the new ones marked with (* noprune *) :
I tried /* synthesis keep */ and /* synthesis preserve */ from the notes I'd made some time ago - but in my notes I stated that I had problems trying to get nodes to appear and the only way I could get it to work was to make output signals in the module header instead.
Does it only work with the reg keyword perhaps?
