Forum Discussion
ContributorMaking Nodes visible to SignalTap
I tried (* preserve_for_debug *) in VgaDisplay.sv but that still won't show vic_screen_lines in STP. I tried "Design Filter (all names)" as well - it still doesn't appear when I click List.
It is not listed in the 2 optimization result reports for removal, I can't find it in the compilation output, and I certainly can't see it in the RTL Viewer so it must have been removed somehow.
BUT.. I have just this minute tried searching for *vic_screen_lines* - and it appears! So I will have to remind myself to always use the asterisks either side of the node. I feel so stupid now - thank you for joining on me on this journey.
Always surround with asterisks, Sparky! Always!
Super ContributorWhat logic are those nodes connected to? There must be a reason why they are not showing up in the Node Finder.
Also, what does editing your design in Notepad have to do with creating assignments for your Quartus project in the Assignment Editor?
ContributorThe only reason I mentioned Notepad is that I find editing text faster than going into the Quartus UI screens. Just saying that if I can "decorate" registers/nodes withing the Verilog text, that's easier than fiddling with the Assignment Editor.. However.. I do seem to have hit the pin limit where I may need to do what you suggested anyway:
What is my logic connected to? Well.. I had hardcoded a load of constants that need to become variable. Once I did that, the logic didn't seem to work the way I expected it to so I thought I would "promote" the nodes to outputs so I can see what values they are taking on in SignalTap..
Maybe I have far too many interdependencies here and perhaps I need to take a step back and simplify what I have.
The last 5 signals I refer to in my VGAController module - it decides where to paint a border or a screen background.. as the old Commodore Vic 20 used to.
I know what I am doing it bad because I am including so much arithmetic now. It wouldn't have mattered with the constants.. but pretty bad to implement that complicated mess in logic.
