Forum Discussion
ContributorMaking Nodes visible to SignalTap
I tried (* preserve_for_debug *) in VgaDisplay.sv but that still won't show vic_screen_lines in STP. I tried "Design Filter (all names)" as well - it still doesn't appear when I click List.
It is not listed in the 2 optimization result reports for removal, I can't find it in the compilation output, and I certainly can't see it in the RTL Viewer so it must have been removed somehow.
BUT.. I have just this minute tried searching for *vic_screen_lines* - and it appears! So I will have to remind myself to always use the asterisks either side of the node. I feel so stupid now - thank you for joining on me on this journey.
Always surround with asterisks, Sparky! Always!
ContributorWhen you say "registering those signals", what do you actually mean, sorry?
Here's another case for example:
bit [7:0] vic_screen_lines; assign vic_screen_lines = vicScreenCharHeight << 3;
I have other assign statements that use vic_screen_lines but I cannot view them in SignalTap.
I tried this too but it made no difference:
(* noprune *) reg [7:0] vic_screen_lines;
Super Contributor- SparkyNZ
Oh, so if the registers aren't modified on a clock cycle (ie. within an always block or state machine), then maybe registers are not inferred? Is it possibly because I have "continuous" logic here rather than clocked (flip-flop) logic?
Please excuse my limited experience - I'm still a beginner/dabbler. Maybe it would be good for me to scale down a smaller project and see what is actually produced in the RTL Viewer.
