Forum Discussion
ContributorMaking Nodes visible to SignalTap
I tried (* preserve_for_debug *) in VgaDisplay.sv but that still won't show vic_screen_lines in STP. I tried "Design Filter (all names)" as well - it still doesn't appear when I click List.
It is not listed in the 2 optimization result reports for removal, I can't find it in the compilation output, and I certainly can't see it in the RTL Viewer so it must have been removed somehow.
BUT.. I have just this minute tried searching for *vic_screen_lines* - and it appears! So I will have to remind myself to always use the asterisks either side of the node. I feel so stupid now - thank you for joining on me on this journey.
Always surround with asterisks, Sparky! Always!
Super ContributorHi,
I try with either reg/logic without clocking like below, but still can find the node in STP.
reg/logic [3:0] intermediate;
assign intermediate = a & b;
assign y = intermediate ^ a;
Have you try preserve for debug check this link https://www.intel.com/content/www/us/en/docs/programmable/683236/21-3/preserving-signals-for-monitoring-and.html?
In STP, may be can use the filter Design Filter (all names).
Have you check the optimization result report, does the nodes being optimized away?
SparkyNZI tried (* preserve_for_debug *) in VgaDisplay.sv but that still won't show vic_screen_lines in STP. I tried "Design Filter (all names)" as well - it still doesn't appear when I click List.
It is not listed in the 2 optimization result reports for removal, I can't find it in the compilation output, and I certainly can't see it in the RTL Viewer so it must have been removed somehow.
BUT.. I have just this minute tried searching for *vic_screen_lines* - and it appears! So I will have to remind myself to always use the asterisks either side of the node. I feel so stupid now - thank you for joining on me on this journey.
Always surround with asterisks, Sparky! Always!
