How do I do line by line timing analysis in Quartus Prime Timing Analyzer?

I am familiar with the following timing analysis flow:

1. Write an HDL design file (mostly .sv or .v).
2. Simulate it.
3. Integrate it into the project.
4. Do synthesis, Fitter.
5. Open timing analyzer -> Setup Summary / Top failing paths.

When I do such things, I find that there is a negative setup slack at one of the registers which gets its value from FW, and this value comes from a different clock domain (clocked by a different clock at different frequency). This register is only updated when FW runs some script periodically.

The output of this register goes further down to logic which has several combinational and Boolean operators expressed as a conditional statement, which indicates that the logic down the line is going to consume more resources.

If I sort the timing analyzer view by the delay at each level, I see that some of the conditional blocks as above are having more delay but they also have a positive slack. I am curious that if I simplify those expressions to have less logic, will this compensate the negative slack on the register from which these blocks get their input?

What I see is that, the timing analyzer has a number of launch and latch nodes, which I can locate in the design file. What I want is that I have design file, I want to select a specific signal (reg/wire) as a node and I want to know the gate delay of any expression, for ex:

assign output = ((count_1 >= (reg_1 + 1)) && (count_2 <= (reg_2 - 2)));

All of the LHS signals are either regs or wires driven by regs. This expression will have outputs of two comparators ANDed together, so I want to know the combinational delay from the (reg_1 + 1) till the output, so that I can do some adjustments/tweaking/optimization or divide this logic into multiple registered levels.

I want to go from variables -> nodes -> delays. Currently it is: Failed path -> Nodes (with delays) -> variables (locate in design file).