About the "set_false_path" command

1) It's a "false path" in so far as the indicated analysis is not performed on the path in question. Normally, set_false_path with no options prevents all analysis on a path (a true cut/false path). Using -setup with it, for example, means that hold analysis will still be performed but setup analysis will not.

2) Yes, that's exactly how you would do it. No, you would almost never false path a clock path. That still has to launch data to the next register.

Should be no problem to use the sdc constraint, if there a problem, you will see the constraint being ignored in the Report Ignored SDC in the Timing Analyzer.

Let me add more info:

The set_false_path command tells the timing analyzer not to analyze a path or group of paths. It can be between keepers (registers, I/Os, etc.) or between clocks.

The -from and -to values are collections of clocks, registers, ports, pins, or cells in the design. If the -from or -to values are not specified, the collection is converted automatically into [get_keepers *]

When the constraint is applied to clocks, then all paths that are clocked by the respective clock will not be analyzed.

Three examples:

# Cut timing from an input port to all of its destinations:

set_false_path -from [get_ports reset_button]

# Cut timing from a mode_select register, which is static in the design, to all of its destinations:

set_false_path -from [get_keepers *|mode_select]

# Cut timing from clk_a to clk_b:

set_false_path -from [get_clocks clk_a] -to [get_clocks clk_b]

The last example cuts timing on all paths where clock clk_a drives the source register and clock clk_b drives the destination register.

Note that transfers in the other direction have not been cut, and another set_false_path assignment would be necessary- set_false_path -from [get_clocks clk_b] -to [get_clocks clk_a]

Cutting timing between clocks is often best accomplished with set_clock_groups.

Regards,

Richard Tan

1) To set a false path between two clock domains, it is recommended to use:

set_false_path -from [get_clocks clockA] -to [get_clocks clockB]

or

set_clock_group -asynchronous -from [get_clocks A] -to [get_clocks B]

instead of:

set_false_path -from [get_ports {DATA}] -to [get_pins {reg|datain}

You may checkout this youtube video: https://www.youtube.com/watch?v=BNiXxmQlCCs

2. The example 2 that I provided refers to the mode_select register. If you happen to have a mode_select port with the same name as the register, then by using [get_keepers *|mode_select], both may possibly be impacted by the SDC constraints.

While it's technically possible to use the same name for a port and a register, doing so can lead to confusion and make the code harder to understand.

It's generally good practice to use distinct names that clearly convey the purpose of each signal in the design.

Regards,

Richard Tan

Generally the sdc constraints should not be a problem.

Regards,

Richard Tan

Thank you for answering.

Thank you for your kind response.

No problem. Happy to help.

Now, I will transition this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out.

Thank you and have a great day!

Best Regards,

Richard Tan