Should be no problem to use the sdc constraint, if there a problem, you will see the constraint being ignored in the Report Ignored SDC in the Timing Analyzer.
Let me add more info:
The set_false_path command tells the timing analyzer not to analyze a path or group of paths. It can be between keepers (registers, I/Os, etc.) or between clocks.
The -from and -to values are collections of clocks, registers, ports, pins, or cells in the design. If the -from or -to values are not specified, the collection is converted automatically into [get_keepers *]
When the constraint is applied to clocks, then all paths that are clocked by the respective clock will not be analyzed.
Three examples:
# Cut timing from an input port to all of its destinations:
set_false_path -from [get_ports reset_button]
# Cut timing from a mode_select register, which is static in the design, to all of its destinations:
set_false_path -from [get_keepers *|mode_select]
# Cut timing from clk_a to clk_b:
set_false_path -from [get_clocks clk_a] -to [get_clocks clk_b]
The last example cuts timing on all paths where clock clk_a drives the source register and clock clk_b drives the destination register.
Note that transfers in the other direction have not been cut, and another set_false_path assignment would be necessary- set_false_path -from [get_clocks clk_b] -to [get_clocks clk_a]
Cutting timing between clocks is often best accomplished with set_clock_groups.
Regards,
Richard Tan
Occasional Contributor
