Forum Discussion
Occasional ContributorAbout the "set_false_path" command
My apologize for not understand your previous question correctly.
Correct me if I am wrong. This look like asynchronous input to the synchronizer logic.
Setting false path to the [asynchronous input paths to synchronizer logic] (path 1) should be sufficient.
Regards,
Richard Tan
Super Contributor1) To set a false path between two clock domains, it is recommended to use:
set_false_path -from [get_clocks clockA] -to [get_clocks clockB]
or
set_clock_group -asynchronous -from [get_clocks A] -to [get_clocks B]
instead of:
set_false_path -from [get_ports {DATA}] -to [get_pins {reg|datain}
You may checkout this youtube video: https://www.youtube.com/watch?v=BNiXxmQlCCs
2. The example 2 that I provided refers to the mode_select register. If you happen to have a mode_select port with the same name as the register, then by using [get_keepers *|mode_select], both may possibly be impacted by the SDC constraints.
While it's technically possible to use the same name for a port and a register, doing so can lead to confusion and make the code harder to understand.
It's generally good practice to use distinct names that clearly convey the purpose of each signal in the design.
Regards,
Richard Tan
Occasional ContributorThank you for answering.
I'm sorry that I don't have enough words.
What we were envisioning was a circuit like the one shown below, and was not the clock switching that you answered.
The intent of question 1) is whether the following description of the falsity path setting for Target path1 is okay if the data in the figure is completely asynchronous with respect to CLK.
set_false_path -from [get_ports {DATA}] -to [get_pins {reg|datain}
Sorry for the basic question, but I would appreciate it if you could explain it to me.
