5CGXFC5C6 fails verification after reboot

Question

This is a re-post. I'm new to the forum and may have originally posted it in a wrong place, sorry if I broke some rules.

We are using this 5CGXFC5C6 chip for our video card. The FPGA loads okay and passes verification, but if the board gets rebooted, the verification will not pass even though the boards are still working okay. The error messages are:

209062 Flash Loader IP not loaded on device 1

209012 Operation failed

I'm new to the process, anyone can give some explanation? Thanks.

altera_forum · Answer

A couple of questions:

Where does your FPGA boot from - serial/parallel boot ROM, programming cable?

What 'verification' does it pass - is this some run-time check or something related to the FPGA programming?

By 'rebooted' - what do you mean? Soft restart of some internal logic; reconfiguration of FPGA; full power cycle?

How are you determining 'the boards are still working okay' after reboot?

Are you using any Altera IP and do you have the relevant license to use it?

You've not posted in the wrong place but a little more info might help.

Cheers,

Alex

altera_forum · Answer

Dear Alex,

Thanks for the response and the following are the responses from our hardware engineer:

Q. Where does your FPGA boot from - serial/parallel boot ROM, programming cable?

A. Serial Prom

Q. What 'verification' does it pass - is this some run-time check or something related to the FPGA programming?

A. During the programming cycle, using the Quartus programmer, the verify checkbox is active and the programmer does the verification and passes as long as we do not cycle the power.

Q. By 'rebooted' - what do you mean? Soft restart of some internal logic; reconfiguration of FPGA; full power cycle?

A. We power down the board, power back up and using the same Quartus programmer we do a verify and it Fails.

Q. How are you determining 'the boards are still working okay' after reboot?

A. We run video through the card and all works great. The debug leds show the correct blinking status, no underruns, no dropped frames etc.

Q. Are you using any Altera IP and do you have the relevant license to use it?

A. We have an enbedded NIOS in the FPGA. The compiler has been licensed and produces the licensed NIOS code. The test jig that we have is used for programming new boards and also running factory aceptance tests. Part of the factory test includes programming the board. There are two images on the serial prom. The latest image that gets programmed is the one we boot from. In the case where the boot image becomes corrupted due to a power failure during a field upgrade, the second image can be used for booting so we do not brick the card. I do not know if this is related to the verify failure. The dual image mechanisim is implemented in the "File, create programming file" dialog box. There it lists two files. The development engineer produces the .jic file based on these two files / dialog box and submits the output image to test engineering. In test engineering we program/verify the image and also do a video test which outputs video to a monitor.

Regards,

altera_forum · Answer

Have a look at solution id: rd01102012_443 (http://www.altera.com/support/kdb/solutions/rd01102012_443.html). It refers to a different device family but relates to the same error you're seeing.  When the FPGA boots from a Serial PROM there's no concept of verification - other than a successful boot. So, regarding your answers to Q2 &amp; Q3, what is the difference in power-up/start-up sequence between a boot that successfully verifies and a re-boot that fails?  Regards, Alex

altera_forum · Answer

After loading the FPGA from the serial prom (the new image that we just programmed and verified), you should still be able to verify that the data file in the system still matches what has been programmed into the serial prom. We are programming using a .jic file, not an sof.

altera_forum · Answer

Agreed.

So, having programmed your PROM using your .jic file, you power cycle your board. The FPGA configures from the PROM.

Then in the programmer (are you using the GUI or command line?) you open (or keep open) the same .jic file and select the 'verify' tick box next to the PROM in question. Click 'Start'.

Is this the sequence that results in the error code you're seeing?

The error message you're reporting indicates the FPGA is configured with an image that doesn't know how to talk to the serial PROM - i.e. there's no Altera IP in the FPGA that the programmer recognises.

When you try to verify your .jic image, the programmer should first configure the FPGA with the 'Factory default enhanced SFL image', overwriting any configuration image the FPGA booted with. This allows the programmer to talk to the PROM.

Can you be a little more explicit with the steps you're taking when verifying?

Cheers,

Alex

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5CGXFC5C6 fails verification after reboot

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