Forum Discussion
Altera_Forum
Honored Contributor
11 years agoAgreed.
So, having programmed your PROM using your .jic file, you power cycle your board. The FPGA configures from the PROM. Then in the programmer (are you using the GUI or command line?) you open (or keep open) the same .jic file and select the 'verify' tick box next to the PROM in question. Click 'Start'. Is this the sequence that results in the error code you're seeing? The error message you're reporting indicates the FPGA is configured with an image that doesn't know how to talk to the serial PROM - i.e. there's no Altera IP in the FPGA that the programmer recognises. When you try to verify your .jic image, the programmer should first configure the FPGA with the 'Factory default enhanced SFL image', overwriting any configuration image the FPGA booted with. This allows the programmer to talk to the PROM. Can you be a little more explicit with the steps you're taking when verifying? Cheers, Alex