Honored Contributor
Honored ContributorDear Alex,
Thanks for the response and the following are the responses from our hardware engineer: Q. Where does your FPGA boot from - serial/parallel boot ROM, programming cable? A. Serial Prom Q. What 'verification' does it pass - is this some run-time check or something related to the FPGA programming? A. During the programming cycle, using the Quartus programmer, the verify checkbox is active and the programmer does the verification and passes as long as we do not cycle the power. Q. By 'rebooted' - what do you mean? Soft restart of some internal logic; reconfiguration of FPGA; full power cycle? A. We power down the board, power back up and using the same Quartus programmer we do a verify and it Fails. Q. How are you determining 'the boards are still working okay' after reboot? A. We run video through the card and all works great. The debug leds show the correct blinking status, no underruns, no dropped frames etc. Q. Are you using any Altera IP and do you have the relevant license to use it? A. We have an enbedded NIOS in the FPGA. The compiler has been licensed and produces the licensed NIOS code. The test jig that we have is used for programming new boards and also running factory aceptance tests. Part of the factory test includes programming the board. There are two images on the serial prom. The latest image that gets programmed is the one we boot from. In the case where the boot image becomes corrupted due to a power failure during a field upgrade, the second image can be used for booting so we do not brick the card. I do not know if this is related to the verify failure. The dual image mechanisim is implemented in the "File, create programming file" dialog box. There it lists two files. The development engineer produces the .jic file based on these two files / dialog box and submits the output image to test engineering. In test engineering we program/verify the image and also do a video test which outputs video to a monitor. Regards,
