Honored Contributor
Honored ContributorI think I see...
In order to verify the contents of the EPCS the FPGA must be configured with and image containing IP that can talk to it. When you're programming the device, as per your 1st trace, the following lines relate to the configuration of the FPGA: --- Quote Start --- Info (209016): Configuring device index 1 Info (209017): Device 1 contains JTAG ID code 0x02B020DD Info (209007): Configuration succeeded -- 1 device(s) configured --- Quote End --- The FPGA is now able to control the EPCS and goes on to program it: --- Quote Start --- Info (209018): Device 1 silicon ID is 0x16 Info (209044): Erasing ASP configuration device(s) Info (209019): Blank-checking device(s) Info (209023): Programming device(s) Info (209021): Performing CRC verification on device(s) Info (209011): Successfully performed operation(s) --- Quote End --- Your second and third traces do not perform first step above - they do not configure the FPGA and go straight on and attempt to check the EPCS. The second trace shows a pass because the FPGA remains configured with the factory programming image from your previous programming step. The third trace fails because the FPGA has booted from the EPCS and your user FPGA image does not contain the IP the programmer needs to control the EPCS. So, the fix. When you are trying to verify the EPCS from a power up you need to ensure the 'Program/Configure' check box, next to the 'Factory default enhanced SFL image', is ticked (as well as the verify check box next to the EPCS64 - see attached image). This will force the programmer to configure the FPGA with an image containing the necessary IP before it tries to check the contents of the EPCS. Cheers, Alex
