Forum Discussion
Altera_Forum
Honored Contributor
11 years agoHave a look at solution id: rd01102012_443 (http://www.altera.com/support/kdb/solutions/rd01102012_443.html). It refers to a different device family but relates to the same error you're seeing.
When the FPGA boots from a Serial PROM there's no concept of verification - other than a successful boot. So, regarding your answers to Q2 & Q3, what is the difference in power-up/start-up sequence between a boot that successfully verifies and a re-boot that fails? Regards, Alex