Avalon bus timing question

I'm trying to understand exactly when the chip select and read/write lines on the Avalon bus change. For a standard write transfer the timing shows the chip select coming high after the address and data and the write lines are set up. The chip select goes low after the transfer is complete. However, the manual states that the chip select line shouldn't be used as a trigger and the rising edge of the clock should be used instead.

So far so good but I'm using flow control and wait states for my interface (FTDI 245BM) since I have to monitor the status lines on the external chip and can't assume that each read/write finishes in one cycle.

My question: can I rely on the chip select line becoming inactive or the read/write strobes changing when I use the readyfordata signal to hold off the transfers? Otherwise I don't really know when I should start the next transfer.

The current design uses chip select as a trigger but works only when the clock frequency and wait states are set up just right. I'd like to make things a little cleaner but can't figure out how I can know when the next transfer should start. Can I rely on the chip select or read/write signals to change before the next cycle starts? This device does both reading and writing to a constant address so I'm really only worried about figuring out when the transfers start and stop, not so much about when to latch address and data.

Thanks,

Andrew