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Altera_Forum
Honored Contributor
Honored ContributorAvalon bus timing question
I'm trying to understand exactly when the chip select and read/write lines on the Avalon bus change. For a standard write transfer the timing shows the chip select coming high after the address a...
Altera_ForumHonored Contributor
Honored ContributorUse variable wait states, and don't use CS, it's redundant for a simple peripheral. Simply assert waitrequest IMMEDIATELY upon seeing either READ or WRITE being asserted, and then take your time, deassert waitrequest and the next cycle everything will be over. While you have waitrequest asserted, READ or WRITE should be asserted as well; this proves that the avalon bus is holding off for you.
