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Altera_Forum's avatar
Altera_Forum
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20 years ago

Avalon bus timing question

I'm trying to understand exactly when the chip select and read/write lines on the Avalon bus change. For a standard write transfer the timing shows the chip select coming high after the address a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
19 years ago

<div class='quotetop'>QUOTE </div>

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I don&#39;t really want to hold off the transfer for minutes at a time with waitrequest so I think I&#39;ll use flow control instead.[/b]

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As far as I can tell, there isn&#39;t any difference to the master whether you hold it with waitrequest or with dataavailable. According to the Avalon spec, a master doesn&#39;t directly receive dataavailable or dataready, it just gets blocked on waitrequest, (the same as per variable wait state).

I can see the flow control being slightly easier to implement if you already have a fixed wait state port -- but the end result will be the same to the master.

If you want to avoid having the master block for an indeterminate time on reads, you need to come up with a different mechanism.