Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorAvalon bus timing question
I'm trying to understand exactly when the chip select and read/write lines on the Avalon bus change. For a standard write transfer the timing shows the chip select coming high after the address a...
Altera_ForumHonored Contributor
Honored ContributorThat sounds easy, I just looked at the timing diagram in the avalon manual and it's pretty clear except for what happens after the transfer terminates (at point J, in the figures).
Since the read/write strobes are still active at the rising edge that terminates the transfer, how will I know whether the bus is requesting another cycle right away or not?
