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Altera_Forum's avatar
Altera_Forum
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20 years ago

Avalon bus timing question

I'm trying to understand exactly when the chip select and read/write lines on the Avalon bus change. For a standard write transfer the timing shows the chip select coming high after the address a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
20 years ago

Hi queisser,

> Simply assert waitrequest IMMEDIATELY upon seeing either READ or WRITE

> being asserted,

In some designs, I've found it convenient to leave waitrequest asserted, then

negate the signal once everything is ready -- asserting again immediately after

the clock edge that completes the cycle.

> how will I know whether the bus is requesting another cycle right away or not?

You will know on the next rising edge. The cycle is completed on the rising edge

where waitrequest is negated.

Regards,

--Scott