Avalon bus timing question

Hi queisser,

> and the rising edge after that starts the next cycle?

That depends on the state of the control signals ... and how you define "next cycle".

Basically, the rising edge where waitrequest is negated completes the current

"bus cycle" (the data is latched, for example on a read). The rising edge that

completes one bus cycle can be the start of the next. If read remains asserted,

the _following_ rising edge can potentially complete the next cycle (if waitrequest

is negated).

Regards,

--Scott