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Altera_Forum
Honored Contributor
Honored ContributorAvalon bus timing question
I'm trying to understand exactly when the chip select and read/write lines on the Avalon bus change. For a standard write transfer the timing shows the chip select coming high after the address a...
Altera_ForumHonored Contributor
Honored ContributorHi queisser,
> and the rising edge after that starts the next cycle? That depends on the state of the control signals ... and how you define "next cycle". Basically, the rising edge where waitrequest is negated completes the current "bus cycle" (the data is latched, for example on a read). The rising edge that completes one bus cycle can be the start of the next. If read remains asserted, the _following_ rising edge can potentially complete the next cycle (if waitrequest is negated). Regards, --Scott
