Avalon bus timing question

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originally posted by smcnutt@Mar 14 2006, 08:34 AM

hi queisser,

> and the rising edge after that starts the next cycle?

that depends on the state of the control signals ... and how you define "next cycle".

basically, the rising edge where waitrequest is negated completes the current

"bus cycle" (the data is latched, for example on a read). the rising edge that

completes one bus cycle can be the start of the next. if read remains asserted,

the _following_ rising edge can potentially complete the next cycle (if waitrequest

is negated).

regards,

--scott

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Ok, thanks, that confirms what I thought. I think I&#39;m back to using flow control since I can never know when my peripheral (the FTDI USB fifo chip) will be able to produce data. I don&#39;t really want to hold off the transfer for minutes at a time with waitrequest so I think I&#39;ll use flow control instead. From the manual it appears that that&#39;s the recommended way of doing it.

Andrew