Forum Discussion
Altera_Forum
Honored Contributor
20 years agoAvalon bus timing question
I'm trying to understand exactly when the chip select and read/write lines on the Avalon bus change. For a standard write transfer the timing shows the chip select coming high after the address a...
Altera_Forum
Honored Contributor
20 years ago --- Quote Start --- originally posted by jdhar@Mar 9 2006, 05:15 PM if you use the waitrequest signal, you can stall the bus altogether and you decide when the transfers occur. is this the functionality you are looking for?
<div align='right'><{post_snapback}> (index.php?act=findpost&pid=13269)
--- quote end ---
--- Quote End --- Yes, that's probably what I should be doing. I looked through all the different options of Avalon cycles and the variable wait state is probably the best fit. Right now I'm using setup,wait and hold with fixed amounts but waitrequest would be cleaner. I'm still a little unclear about when the strobes and chip select change. In the documentation for the transfers with flow control the control signals may just stay in one state and back-to-back transfers occur on the rising clk. Since my peripheral is so slow there can't be any back-to-back transfers and I'm wondering if the control signals are guaranteed to change state in that case. Andrew