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Altera_Forum
Honored Contributor
Honored ContributorAvalon bus timing question
I'm trying to understand exactly when the chip select and read/write lines on the Avalon bus change. For a standard write transfer the timing shows the chip select coming high after the address a...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- originally posted by smcnutt@Mar 11 2006, 08:25 AM you will know on the next rising edge. the cycle is completed on the rising edge
where waitrequest is negated.
regards,
--scott
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--- quote end ---
--- Quote End --- Ahh, so the rising edge where waitrequest is negated completes the cycle and the rising edge after that starts the next cycle?
