ContributorHi Team,
I am using ddr3 IP controller in my design which operates at 200Mhz (avalon clock) and configured memory clock as 400 Mhz.
With that settings when I compile the design, I am getting negative slack for ddr3 core setup. some paths are reported which are in ddr3 library files.
Please give some solution for this issue.
Super ContributorWhat's the target device, and if needed for it, did you run the Tcl script needed to set the appropriate assignments? What version of Quartus? What are your EMIF IP parameter settings? What board is this for, custom or a dev kit? Really need way more info here.
ContributorHi,
Target device : Cyclone v gx(5CGXFC5C6F27C7)
Yes i run the tcl script which is generated in the directory.(assigments.tcl,timing.tcltiming_ccore.tcl)
Quartus version is 22.1 prime standard
Custom board.
The following setting are used in EMIF IP:
input ref clock for ddr3 is 50 Mhz clock from board oscillator, connected in qsys design.
Please let me know if you need any additional details .
Regular ContributorHello,
"input ref clock for ddr3 is 50 Mhz clock from board oscillator, connected in qsys design."
Regards,
Adzim
ContributorHi,
yes, input clk is from board oscillator and ddr ref clk is connected to that only in qsys.
this is how it is connected. Are u suggesting to connect the pll_ref_clk directly with inclk from top ?
Regular ContributorHi
"Are u suggesting to connect the pll_ref_clk directly with inclk from top ?"
What is the other component that used that clock connection?
Regards,
Adzim
Contributorhi ,
Ok i will check and let you know.
only ddr3, ethernet ip, pll is using that clock source only. that also connected through qsys clock source.
ContributorHi AdzimZM_Intel,
With that clock implementation also, timing violation is increased.
attached the archived project which contains the ddr_clk connected to top.
With that also tming violation is there..Please check
Regular ContributorHi
Please revert back the change. It's introducing more timing violation.
To help in fix the timing issue, please change the compiler setting in advanced setting (synthesis) for optimization technique to speed.
Please supply the afi_clk from ddr3 module to cpu and vic_0 module.
Regards,
Adzim
ContributorOK I will check and let you know the results
Thanks for suggestion
ContributorHi,
I have modified as you have suggested(optimization- speed) ,afi_clk to cpu,vic.
With that also timing violations are reported for ddr set up.
PLease check the attached project archive for reports
New ContributorI was getting timing violations with my emif design until I found this: https://www.intel.com/content/www/us/en/support/programmable/articles/000078771.html.
In my case, I moved the qsys qip file before the sdc files in the qsf. I also had to modifiy the qsys qip file to move the ddr3_emif sdc file before the other sdc files in the qip.
Hope that helps.
ContributorThanks for your response.
But i am compiling the design with the files order setup only.(first qip file then sdc file)
Still ddr has timing violation particularly for ddr3 memory clk as 400 and controller rate is 200.
