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SERMASWATHIKA's avatar
SERMASWATHIKA
Icon for Contributor rankContributor
1 year ago

timing violation on ddr3 setup

Hi Team, I am using ddr3 IP controller in my design which operates at 200Mhz (avalon clock) and configured memory clock as 400 Mhz. With that settings when I compile the design, I am getting ne...
Memory
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hi


Please revert back the change. It's introducing more timing violation.


To help in fix the timing issue, please change the compiler setting in advanced setting (synthesis) for optimization technique to speed.

Please supply the afi_clk from ddr3 module to cpu and vic_0 module.



Regards,

Adzim


SERMASWATHIKA's avatar
SERMASWATHIKA
Icon for Contributor rankContributor
1 year ago

Hi,

I have modified as you have suggested(optimization- speed) ,afi_clk to cpu,vic.

With that also timing violations are reported for ddr set up.

PLease check the attached project archive for reports