Forum Discussion
SERMASWATHIKA
Contributor
Contributortiming violation on ddr3 setup
Hi Team, I am using ddr3 IP controller in my design which operates at 200Mhz (avalon clock) and configured memory clock as 400 Mhz. With that settings when I compile the design, I am getting ne...
sstrell
Super Contributor
Super ContributorWhat's the target device, and if needed for it, did you run the Tcl script needed to set the appropriate assignments? What version of Quartus? What are your EMIF IP parameter settings? What board is this for, custom or a dev kit? Really need way more info here.
SERMASWATHIKAContributor
ContributorHi,
Target device : Cyclone v gx(5CGXFC5C6F27C7)
Yes i run the tcl script which is generated in the directory.(assigments.tcl,timing.tcltiming_ccore.tcl)
Quartus version is 22.1 prime standard
Custom board.
The following setting are used in EMIF IP:
input ref clock for ddr3 is 50 Mhz clock from board oscillator, connected in qsys design.
Please let me know if you need any additional details .
