Contributor
New ContributorI was getting timing violations with my emif design until I found this: https://www.intel.com/content/www/us/en/support/programmable/articles/000078771.html.
In my case, I moved the qsys qip file before the sdc files in the qsf. I also had to modifiy the qsys qip file to move the ddr3_emif sdc file before the other sdc files in the qip.
Hope that helps.
ContributorThanks for your response.
But i am compiling the design with the files order setup only.(first qip file then sdc file)
Still ddr has timing violation particularly for ddr3 memory clk as 400 and controller rate is 200.
