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SERMASWATHIKA's avatar
SERMASWATHIKA
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2 years ago

timing violation on ddr3 setup

Hi Team, I am using ddr3 IP controller in my design which operates at 200Mhz (avalon clock) and configured memory clock as 400 Mhz. With that settings when I compile the design, I am getting ne...
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AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi


"Are u suggesting to connect the pll_ref_clk directly with inclk from top ?"

  • Yes, is that possible?


What is the other component that used that clock connection?


Regards,

Adzim


  • SERMASWATHIKA's avatar
    SERMASWATHIKA
    Icon for Contributor rankContributor
    2 years ago

    hi ,

    Ok i will check and let you know.

    only ddr3, ethernet ip, pll is using that clock source only. that also connected through qsys clock source.

  • SERMASWATHIKA's avatar
    SERMASWATHIKA
    Icon for Contributor rankContributor
    2 years ago

    Hi AdzimZM_Intel,

    With that clock implementation also, timing violation is increased.

    attached the archived project which contains the ddr_clk connected to top.

    With that also tming violation is there..Please check