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SERMASWATHIKA's avatar
SERMASWATHIKA
Icon for Contributor rankContributor
2 years ago

timing violation on ddr3 setup

Hi Team, I am using ddr3 IP controller in my design which operates at 200Mhz (avalon clock) and configured memory clock as 400 Mhz. With that settings when I compile the design, I am getting ne...
Memory
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hello,


"input ref clock for ddr3 is 50 Mhz clock from board oscillator, connected in qsys design."

  • Can you provide this connection in the QSYS?


Regards,

Adzim


  • SERMASWATHIKA's avatar
    SERMASWATHIKA
    Icon for Contributor rankContributor
    2 years ago

    Hi,

    yes, input clk is from board oscillator and ddr ref clk is connected to that only in qsys.

    this is how it is connected. Are u suggesting to connect the pll_ref_clk directly with inclk from top ?