Forum Discussion

Geats_X's avatar
Geats_X
Icon for New Contributor rankNew Contributor
12 months ago

problem to use F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express*

Hi, I want to use F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* to generate a demo with gen3 1x4 mode. When I was compiling, the following error occurred: Error(22728): Synthesis is run on design with Tile IP for instance "pcie_inst|pcie_avst_f_0" of entity "pcie_pcie_avst_f_1210_rb4ao6i" but the support logic has not been generated.

Error(22728): Synthesis is run on design with Tile IP for instance "sys_pll_inst|systemclk_f_0" of entity "pcie_sys_pll_systemclk_f_310_n6wsqji" but the support logic has not been generated. Did I miss the configuration parameters in the IP, or do I need to design the logic for the Avalon ST bus?

Because the example design does not support gen3 1x4 mode, and the PIO module in the design also does not support gen3 1x4. If this is the case, please let me know how to modify it, thank you in advance.

Here is my parameters:

 

Pcie

14 Replies

    • Geats_X's avatar
      Geats_X
      Icon for New Contributor rankNew Contributor
      12 months ago

      Hi Rong,

      I'm using quartus prime pro 24.2 on linux.

  • RongY_altera's avatar
    RongY_altera
    Icon for Contributor rankContributor
    12 months ago

    You can generate a PIO example design based on Gen3 1x16 first. Then go into that generated design, modify the PCIe to Gen3 1x4, and click "Generate HDL". After this, you can do a full compilation. I see no critical issue reported in this process.

    Regards,

    Rong

    • Geats_X's avatar
      Geats_X
      Icon for New Contributor rankNew Contributor
      12 months ago

      But in the design of Gen3 1x16, the PIO module only supports 256 bit or 512 bit, while the bit width of Gen3 1x4 is 128 bit. I don't know how to use it when it's 128 bit.

      • RongY_altera's avatar
        RongY_altera
        Icon for Contributor rankContributor
        12 months ago

        The 128/256/512 bit means the data width for user logic.

        Regards,

        Rong

  • RongY_altera's avatar
    RongY_altera
    Icon for Contributor rankContributor
    12 months ago

    If the errors you posted is due to the replacement of pio and mem with your own user logic, we may need to check your design connections.

    PIO design is provided as a starting point for learning the basic mem read/write.

    Regards,

    Rong

    • Geats_X's avatar
      Geats_X
      Icon for New Contributor rankNew Contributor
      12 months ago

      ok, Rong. Thanks for your reply. I'll try to modify my design first.

    • Geats_X's avatar
      Geats_X
      Icon for New Contributor rankNew Contributor
      12 months ago

      I have another question regarding device AGIB041R31B1I2VC, when I want to assign pin_perst_n to PIN_CG52. Why does PIN_PLANER display 'Editing location assignment is not successful. Not assignable'? The pins of PCIE tx and rx PCIe are all assigned in BANK12A.

    • Geats_X's avatar
      Geats_X
      Icon for New Contributor rankNew Contributor
      12 months ago

      When I assign PIN_T59 of bank12c, it will also display 'Editing location assignment is not successful. Not assignable'.

  • RongY_altera's avatar
    RongY_altera
    Icon for Contributor rankContributor
    12 months ago

    Maybe this conflicts with other pins. Comment all pins in qsf and let Quartus assign them for you.


    • Geats_X's avatar
      Geats_X
      Icon for New Contributor rankNew Contributor
      12 months ago

      ok, thank you, Rong. I have no further questions.